The present invention relates to a solid-state imaging device using an amplification-type MOS sensor designed to amplify a signal charge in each cell, and a system using the solid-state imaging device.
With the advances in the semiconductor device technologies, video cameras have become smaller and portable and have been widely used. For the sake of portability, electronic equipment uses a battery as a power supply. Conventionally, video cameras have used CCD sensors as imaging elements. A CCD sensor, however, requires a plurality of types of voltages to drive the device, and hence requires a power supply circuit for generating such voltages from the battery voltage. This interferes with a further reduction in the size of the video camera and a reduction in power consumption.
Studies on compact, lightweight video cameras have been made to make the devices easier to handle. In addition, solid-state imaging devices with larger numbers of pixels have been developed to obtain high-quality images. To realize compact, lightweight video cameras, strong demands have arisen for solid-state imaging devices which allow reductions in power consumption and voltage as well as a reduction in size.
To simply realize a compact solid-state imaging device with a large number of pixels, the pixel size may be reduced. If, however, the pixel size is reduced, the amount of signal charge processed per pixel decreases. As a result, the dynamic range of the solid-state imaging device narrows, and a clear, high-resolution video cannot be obtained.
A CCD uses a plurality of types of voltages as driving voltages for the device, and hence a simple system cannot be coped with in terms of camera system configuration and handling. That is, for application to portable cameras and personal computer cameras, a solid-state imaging device which attains a high S/N ratio and uses a single power supply, and also attains reductions in power consumption and voltage is required. The CCD, however, cannot be driven by a single power supply, and cannot attain reductions in power consumption and voltage. Furthermore, since the S/N ratio decreases as the pixel size decreases, the above requirements cannot be met.
Studies on other devices which can satisfy the above requirements show that an MOS sensor using an amplification-type transistor is available as a solid-state imaging device which can be driven by a single power supply.
This solid-state imaging device is designed to amplify a signal detected by a photodiode in each cell by using a transistor, and is characterized by having a high sensitivity.
Unlike a CCD sensor manufactured by a special manufacturing process, an MOS sensor is manufactured by an MOS process which is widely used for a semiconductor memory such as a DRAM, a processor, and the like. An MOS sensor can therefore be formed on the same semiconductor chip on which a semiconductor memory and a processor are formed, or easily allows sharing of a manufacturing line with a semiconductor memory or a processor.
In the above conventional MOS sensor (amplification-type MOS sensor) using an amplification transistor, it is difficult to reduce luminance irregularity called fixed pattern noise, as will be described later. In addition, the output dynamic range of this amplification-type MOS sensor is as narrow as about 60 dB, which is insufficient as compared with the dynamic range of a silver-halide photographic film, which is 90 dB, and that of a CCD sensor, which is 70 dB. In practice, therefore, considerable limitations are imposed, in terms of image quality, in mounting the amplification-type-MOS sensor in image system equipment such as a video camera.
FIG. 1 is a circuit diagram showing a conventional solid-state imaging device using an amplification-type MOS sensor. Unit cells P0-i-j corresponding to pixels are arranged in the form of a two-dimensional matrix. Although FIG. 1 shows only a 2×2 matrix, the actual apparatus has several thousand cells×several thousand cells. Reference symbol i denotes a variable in the horizontal (row) direction; j, a variable in the vertical (column) direction. Each unit cell P0-i-j is constituted by a photodiode 1-i-j, an amplification transistor 2-i-j, a vertical selection transistor 3-i-j, and a reset transistor 4-i-j. A vertical address circuit 5 and a horizontal address circuit 13 are arranged to sequentially select unit cells P0-1-1, . . . , P0-i-j, . . . which are arranged in the form of a two-dimensional matrix. The vertical address circuit 5 has pairs of address output terminals and reset signal terminals which correspond to n representing the number of horizontal arrays (the number of arrays in the horizontal (row) direction) of unit cells P0-1-1, . . . , P0-i-j of the n×m two-dimensional matrix. The horizontal address circuit 13 has address output terminals corresponding to m representing the number of vertical arrays (the number of arrays in the vertical (column) direction) of unit cells P0-1-1, . . . , P0-i-j of the n×m two-dimensional matrix. Note that m, n, i, and j are arbitrary integers.
Vertical address lines 6-1, 6-2, . . . sequentially and respectively extend from the vertical address circuit 5 in the horizontal (row) direction along the unit cells P0-1-1, P0-1-2, . . . , P0-2-j, . . . arranged in the horizontal (row direction). Each of the vertical address lines 6-1, 6-2, . . . is connected to a corresponding one of the n address output terminals of the vertical address circuit 5.
Reset signal lines 7-1, 7-2, . . . sequentially and respectively extend from the vertical address circuit 5 in the horizontal (row) direction along the unit cells P0-1-1, P0-1-2, . . . , P0-2-j, . . . arranged in the horizontal (row) direction. Each of the reset signal lines 7-1, 7-2, . . . is connected to a corresponding one of the n reset signal terminals of the vertical address circuit 5.
Vertical signal lines 8-1, 8-2, . . . sequentially and respectively extend from the horizontal address circuit 13 in the vertical direction along the unit cells P0-1-1, P0-1-2, . . . , P0-2-j, . . . arranged in the vertical direction. Each of the vertical signal lines 8-1, 8-2, . . . is connected to a corresponding one of the m address output terminals of the horizontal address circuit 13.
The vertical address lines 6-1, 6-2, . . . horizontally extending from the vertical address circuit 5 are connected to the gates of the vertical selection transistors 3-1-1, . . . of the unit cells in the respective rows to determine horizontal lines for reading out signals. Similarly, the reset signal lines 7-1, 7-2, . . . horizontally extending from the vertical address circuit 5 are connected to the gates of the reset transistors 4-1-1, . . . in the corresponding rows.
The photodiode 1-i-j for detecting incident light forms a light-receiving portion for detecting incident light, and generates a signal charge corresponding to the amount of light received. One photodiode forms one pixel. The amplification transistor 2-i-j amplifies the signal charge generated by the photodiode 1-i-j, and outputs the resultant charge as a detection signal. The cathode of the photodiode 1-i-j is connected to the gate of the amplification transistor 2-i-j to amplify the signal charge from the photodiode 1-i-j and generate an amplified output corresponding to the signal charge on the drain side as a detection signal.
The source-drain path of the vertical selection transistor 3-i-j is connected between a DC system power supply and the drain of the amplification transistor 2-i-j. The gate of the vertical selection transistor 3-i-j is connected to the vertical address line 6-j of the vertical address circuit 5.
The reset transistor 4-i-j has a source-drain path connected between the DC system power supply and the cathode of the photodiode 1-i-j, and is operated to reset the signal charge in the photodiode 1-i-j.
More specifically, the source of the vertical selection transistor 3-i-j and the source of the reset transistor 4-i-j are commonly connected to the drain voltage terminal of the DC system power supply to receive a drain voltage.
As described above, the vertical address lines 6-1, 6-2, . . . horizontally extending from the vertical address circuit 5 are connected to the gates of the vertical selection transistors 3-1-1, . . . of the unit cells in the respective rows to determine horizontal lines for reading out signals. Similarly, the reset signal lines 7-1, 7-2, . . . horizontally extending from the vertical address circuit 5 are connected to the gates of the reset transistors 4-1-1, . . . in the respective rows.
In a read operation for the n×m arrangement (n (rows)×m (column) matrix), the vertical address circuit 5 operates to sequentially activate the vertical address lines 6-1, 6-2, . . . so as to activate the n horizontal lines (the lines in the row direction) in the read scanning order, and to output signals to the output terminals so as to reset the signal charges in the pixels.
The above arrangement is associated with an image detection portion. In addition to this image detection portion, this apparatus includes an output portion for reading out the image detected by the image detection portion. The output portion is constituted by load transistors 9-1, 9-2, . . . , signal transfer transistors 10-1, 10-2, . . . , storage capacitors 11-1, 11-2, . . . , and horizontal (row) selection transistors 12-1, 12-2, . . . . The output portion has the following arrangement.
The sources of the amplification transistors 2-1-1, 2-1-2, . . . of the unit cells in the respective columns are respectively connected to the vertical signal lines 8-1, 8-2, . . . , which are arranged in the column direction, in the corresponding columns. Each of the load transistors 9-1, 9-2, . . . is provided for the unit cell in a corresponding one of the columns. One end of each of the vertical signal lines 8-1, 8-2, . . . is connected the DC system power supply through a corresponding one of the load transistors 9-1, 9-2, . . . and the source-drain path thereof.
The other end of each of the vertical signal lines 8-1, 8-2, . . . is connected, through a corresponding one of the signal transfer transistors 10-1, 10-2, . . . for receiving signals corresponding one line, to a corresponding one of the storage capacitors 11-1, 11-2, . . . for storing signals corresponding to one line. The other end of each of the vertical signal lines 8-1, 8-2, . . . is also connected to a signal output terminal (horizontal signal line) 15 through a corresponding one of the horizontal selection transistors 12-1, 12-2, . . . which are selected by horizontal address pulses supplied from the horizontal address circuit 13.
That is, the other end of each of the vertical signal lines 8-1, 8-2, . . . is connected to one end of a corresponding one of the storage capacitors 11-1, 11-2, . . . through the source/drain of a corresponding one of the signal transfer transistors 10-1, 10-2, . . . , and is also connected to the signal output terminal (horizontal signal line) 15 through a corresponding one of the horizontal (row) selection transistors 12-1, 12-2, . . . . The other end of the storage capacitors 11-1, 11-2, . . . is grounded, and the gates of the signal transfer transistors 10-1, 10-2, . . . are connected to a common gate 14. The signal transfer transistors 10-1, 10-2, . . . are turned on by applying a signal transfer pulse to the common gate 14 at the timing at which signal transfer is to be performed. With this operation, voltages appearing on the vertical signal lines 8-1, 8-2, . . . can be transferred to the storage capacitors 11-1, 11-2, . . . and stored therein.
The horizontal address circuit 13 sequentially selects pixel positions corresponding to one horizontal line to be read out. In a pixel read operation for the n×m arrangement (n (rows)×m (columns) matrix), the horizontal address circuit 13 generates horizontal address pulses to activate the horizontal (row) selection transistors 12-1, 12-2, . . . at pixel positions corresponding to the respective scanning positions.
In a pixel read operation for the n×m arrangement (n (rows)×m (columns) matrix), scanning can therefore be controlled such that signals are read out from pixels at the respective lines while the line position is sequentially changed.
The operation of this MOS-type solid-state imaging device will be described below with reference to the timing chart of FIG. 2.
When an address pulse for setting the vertical address line 6-i at high level is applied from the vertical address circuit 5 to the vertical address line 6-i, only the selection transistors 3-i-1, 3-i-2, . . . in this row are turned on. As a result, source follower circuits are constituted by the amplification transistors 2-i-1, 2-i-2, . . . in this row and the load transistors 9-1, 9-2, . . . .
With this operation, the gate voltages of the amplification transistors 2-i-1, 2-i-2, . . . , i.e., voltages almost the same as those of photodiodes 1-i-1, 1-i-2, . . . , appear on the vertical signal lines 8-1, 8-2, . . . .
When a signal transfer pulse is applied to the common gate 14 of the signal transfer transistors 10-1, 10-2, . . . at this time, amplified signal charges represented by the products of the voltages appearing on the vertical signal lines 8-1, 8-2, . . . and the capacitance values of the storage capacitors 11-1, 11-2, . . . are stored in the storage capacitors 11-1, 11-2, . . . .
After the signal charges are stored in the storage capacitors 11-1, 11-2, . . . , the vertical address circuit 5 applies a reset pulse to the reset line 7-i. The reset transistors 4-i-1, 4-i-2, . . . are turned on by this reset pulse, and the signal charges stored in the photodiodes 1-i-1, 1-i-2, . . . are discharged through the reset transistors 4-i-1, 4-i-2, . . . . With this operation, the photodiodes 1-i-1, 1-i-2, . . . are reset.
Horizontal address pulses are sequentially applied from the horizontal address circuit 13 to the horizontal selection transistors 12-1, 12-2, . . . . As a result, the horizontal selection transistors 12-1, 12-2, . . . are kept on while the horizontal address pulses are applied thereto. The signal charges stored in the storage capacitors 11-1, 11-2, . . . are then output from the stored signal output terminal (horizontal signal line) 15 through the horizontal selection transistors 12-1, 12-2, . . . in the ON state. With this operation, image signals corresponding to one line can be obtained as output signals.
By sequentially repeating this operation for the subsequent rows (horizontal lines), all the signals can be read out from the photodiodes arranged two-dimensionally.
By performing read control while changing the line position in this manner, image signals corresponding to one frame can be sequentially extracted. By continuously repeating this operation, a motion image can be obtained.
Each unit cell P0-i-j of the above conventional MOS-type solid-state imaging device always requires three transistors, i.e., the amplification transistor 2-i-j for amplifying a charge signal from the photodiode 1-i-j, the vertical selection transistor 3-i-j for selecting a line for reading out a signal, and the reset transistor 4-i-j for charging/discharging the gate of the amplification transistor 2-i-j. That is, in the conventional MOS-type solid-state imaging device, a three-transistor arrangement is required for one photodiode serving as a light-receiving portion corresponding to a unit pixel. It is therefore difficult to reduce the unit cell size and the size of the imaging device itself.
In addition, since a charge signal is amplified and output by using the amplification transistor 2-i-j, noise is caused by the amplification transistor 2-i-j. The amplification transistor 2-i-j is provided for each unit cell serving as a pixel. Even while no light is incident on the photodiode, the amplification transistor generates an output. This phenomenon is based on a dark current or thermal noise, which cannot be avoided owing to the characteristics of the amplification transistor, and a variation in the threshold voltage. The phenomenon is unique to each pixel of the matrix arrangement and differs among the respective pixels. Therefore, even if uniform light is irradiated on the entire light-receiving surface, the resultant image signals vary in level among the pixels, resulting in an image signal with luminance irregularity. This image with luminance irregularity is called fixed pattern noise because this noise is two-dimensionally distributed, i.e., distributed on a plane called a frame, and is fixed to a certain position. The problem of this noise is serious, and becomes more noticeable with a reduction in pixel size. This arrangement cannot therefore be practically used for an imaging device unless this problem is solved.